1. Field of the Invention
This invention relates to semiconductor devices and more particularly to generating a local clock domain.
2. Description of Background
When running a microprocessor at fast speeds some elements need to run slower than the main processor clock. In fact, large array accesses can take several clock cycles, increasing latency. The current solution to this problem is to send a global signal that acts as a hold signal. The slower element then ignores some of the clock pulses so that a longer time is available. Using a global signal means that the longer cycle times are always at a fixed relationship with this global signal, which means that sometimes cycles are wasted waiting for the global signal.
The current practice is to emit a signal that is used to gate the clock. For example, one signal is propagated throughout the chip. This signal causes the local clock to ignore every other clock cycle. This allows areas of the logic to work at half the frequency of the clock. Similarly, other signals can be sent out to divide the frequency by any integer number.
These gating signals are created globally so that all areas of the chip on a slower frequency work in phase with each other. This has implications for signals that cross the interface between the various clock domains. When a signal from the high frequency area wants to generate an action in a low frequency area, additional latency will occur some of the time. For example, if a signal in the high frequency portion of the logic wants to communicate with logic that is being clocked at one-third of the frequency an average of one cycle is spent at the interface. This comes about when the high frequency request is in phase with the slower frequency; therefore no latency is necessary. Were the high frequency request to come one cycle later, two cycles of latency are necessary to bring the two clock domains in phase. For truly asynchronous operation each of these events is equally likely so there is an average of one full cycle of latency (a min of zero and a max of two).